1. Field of the Invention
The present invention generally relates to communications systems that handle a wide variation in data density, large amplitude jitter with a wide frequency range, and imperfect equalization, such as T1 networks. More particularly, the present invention relates to a timing recovery system including a linear phase-locked loop (“PLL”) with a variable bandwidth loop filter and three proportional paths with non-linear control.
2. Discussion of the Related Art
Networking applications have become popular in recent years, in response to an explosion in the use and variety of networks employed in a vast array of computing settings. Correspondingly, many advances have been made in the related technology in order to improve the quality of these systems. For instance, fully integrated transceivers for T1 Channel Service Unit (“CSU”) and Integrated Services Digital Network (“ISDN”) Primary Rate Interface applications are known in the art, and are presently commercially available. These devices are useful for networking applications, such as timing recovery in T1 systems. However, there are obstacles that prevent such systems from providing good jitter tolerance, a desirable quality in communications networks, and other applications. Such obstacles can include exceptionally large amplitude jitter, a wide variation in data density, large amounts of cable attenuation, and imperfect equalization.
Jitter is the general term used to describe distortion caused by variation of a signal from its reference timing position in a transmission communications system. In an ideal system, bits arrive at time increments that are integer multiples of a bit repetition time. In a real system, however, pulses arrive at times that deviate from these integer multiples. This deviation may cause errors in the transmission of data, particularly when data is transmitted at high speeds. The deviation or variation may be in the amplitude, time, frequency or phase of this data. Jitter may be caused by a number of phenomena, including inter-symbol interference, frequency differences between the transmitter and receiver clock, noise, and the non-ideal behavior of the receiver and transmitter clock generation circuits.
Jitter is a problem of particular import in digital communications systems for several reasons. First, jitter causes the received signal to be sampled at a non-optimal sampling point. This occurrence reduces the signal-to-noise ratio at the receiver and thus limits the information rate. Second, in practical systems, each receiver must extract its received sampling clock from the incoming data signal. Jitter makes this task significantly more difficult. Third, in long distance transmission systems, where multiple repeaters reside in the link, jitter accumulates.
Jitter amplitude is typically measured in unit intervals (“UI”) where 1 UI equals 1 period of bit repetition time. For example, in T1 networks, 1 UI is equal to 648 microseconds and in E1 networks, 1 UI is equal to 488 microseconds. Normal ranges of jitter vary widely depending upon the specific application. For T1 systems, the incoming jitter is generally limited to approximately 5 UI peak-to-peak for jitter frequencies between 10 Hz and 40 KHz, and 0.1 UI peak-to-peak for jitter frequencies between 8 KHz and 40 KHz. However, T1 receivers generally must be able to tolerate sinusoidal jitter with an amplitude as high as 0.4 UI between 10 KHz and 100 KHz, and as large as 28 UI at 300 Hz for network interoperability.
Accordingly, there is a need for a timing recovery system capable of providing improved jitter tolerance, especially for systems that must manage wide variations in data density and large amplitude jitter in large frequency ranges.